1. Field of the Invention
The present invention relates generally to the field of integrated circuits and, more specifically, the present invention relates to a mechanism for testing an integrated circuit.
2. Description of the Related Art
Integrated circuits are becoming more densely packed with increasing numbers of individual circuit elements. It is common for a single chip to have thousands of individual elements that include millions of transistors. With the increasing number of individual elements, testing each element becomes more difficult to achieve. A conventional test mechanism used in the past for testing the integrated circuit is a scan test.
A scan test is typically performed by a scan circuit, also known as a scan cell. The scan circuit usually propagates scan data with test patterns where the test patterns are, subsequently, applied to the inputs of the integrated circuit. Depending on the test pattern, the responses or results of the integrated circuit to the test pattern can provide an accurate indication of the existence or non-existence of defects.
However, with recently developed high-speed circuitry, the scan technology used in the past may be inadequate since a conventional scan circuit is typically too slow for scanning the data through the high-speed circuitry.
A device for testing an integrated circuit includes a self-resetting dynamic circuit having a keeper node and a testing circuit that is coupled to the keeper node. The testing circuit is configured to test the self-resetting dynamic circuit in response to at least one test clock.
Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.